We are pleased to invite you to a Boundary Scan free Workshop that we have organized together with our partner XJTAG. It will be on 18th October in ULMA Embedded Solutions’ facilities in Oñati (map).
This practical, technical workshop is intended for all engineers involved in the design, development, test or production of complex electronic systems, addressing the challenges that OEMs now face.
It is a good opportunity to learn more about Boundary Scan, we will present how this method can improve test coverage and accelerate fault diagnosis on all PCBs, but particularly those that employ BGAs and other devices that use fine-pitch packaging. Attendees will also learn how adopting Boundary Scan can improve the overall design process and significantly reduce PCB re-spins.
During the FREE one-day, hands-on workshop you will learn:
- What JTAG is and how it is used
- How advanced tools can simplify the development of complete tests, using real boards
- How to enable and extend JTAG testing to cover almost an entire board, including non-JTAG devices (such as ADCs, DACs, Flash and DDR)
- How to diagnose and debug faults on failed boards, even under fine-pitch components such as FPGAs or BGAs
Places are limited, so if you are interested in attending, please click here to learn more or REGISTER FOR THE WORKSHOPS. If you need further information, please, don’t hesitate to contact us in marketing@ulmaembedded.com or +34 943 250 300.
NOTE: The course is a hands-on training session and to participate fully you will need to bring a laptop.
AGENDA
| 08:45-09:00 Welcome
| 09:00-09:15 ULMA Presentation
| 09:15-09:45 Introductory presentation
| 09:45-10:00 Introduction to the XJTAG tools
| 10:00-10:30 Communicating with JTAG chain
| 10:30-11:00 Coffee break
| 11:00-12:00 Interacting with JTAG devices
| 12:00-12:15 Introducing board testing with JTAG
| 12:15-12:45 Describing a circuit to enable JTAG testing
| 12:45-13:45 Lunch
| 13:45-14:00 Running an infrastructure connection test
| 14:00-14:15 Introducing testing non-JTAG elements of a board using JTAG
| 14:15-15:15 Implementing tests for non-JTAG elements
| 15:15-15:30 Coffee break
| 15:30-15:45 Presentation to be confirmed
| 15:45-16:15 Close
